----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:16:23 10/11/2013 
-- Design Name: 
-- Module Name:    right_shifter2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity right_shifter is
    Port (	clk : in STD_LOGIC;
				input : in  STD_LOGIC_VECTOR (31 downto 0);
				arthControl : in STD_LOGIC;
				shiftValue : in STD_LOGIC_VECTOR (4 downto 0);
				output : out  STD_LOGIC_VECTOR (31 downto 0));
end right_shifter;

architecture Behavioral of right_shifter is

begin
process(clk)
	variable outputIntermediate : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
	variable shiftBit : STD_LOGIC := '0';
begin

	if clk'event and clk = '1' then
		if arthControl = '1' then
			shiftBit := input(31);
		else
			shiftBit := '0';
		end if;
		
		outputIntermediate := input;
			
		if shiftValue(0) = '1' then
			outputIntermediate := shiftBit & input(31 downto 1);
		end if;
		
		if shiftValue(1) = '1' then
			outputIntermediate := (31 downto 30 => shiftBit) & outputIntermediate(31 downto 2);
		end if;
		
		if shiftValue(2) = '1' then
			outputIntermediate := (31 downto 28 => shiftBit) & outputIntermediate(31 downto 4);
		end if;
		
		if shiftValue(3) = '1' then
			outputIntermediate := (31 downto 24 => shiftBit) & outputIntermediate(31 downto 8);
		end if;
		
		if shiftValue(4) = '1' then
			outputIntermediate := (31 downto 16 => shiftBit) & outputIntermediate(31 downto 16);
		end if;
		output <= outputIntermediate;
	end if;
end process;
end Behavioral;

